Operation speed of semiconductor devices are continuously being improved through development of higher levels of integration. To improve the operation speed, synchronous memory devices which operate in synchronization with an external clock signal from an external circuit have been introduced.
The semiconductor memory device first introduced was a SDR (single data rate) synchronous memory device in which data are inputted and outputted through one data pin for one period of an external clock signal in synchronization with a rising edge of the external clock signal.
However, the SDR synchronous memory device is not sufficient for high-speed systems and therefore a DDR (double data rate) synchronous memory device which processes two data for one period of the external clock signal has been introduced.
In the DDR synchronous memory device, two data are inputted or outputted through a data pin in synchronization with rising and falling edges of the external clock signal. Accordingly, the DDR synchronous memory device has a bandwidth that is twice that of the SDR synchronous memory device, without increasing the clock frequency.
FIG. 1 is a block diagram illustrating a data output circuit of a conventional memory device. Referring to FIG. 1, the conventional data output circuit includes a first data output unit 10, a first data output control unit 12, a second data output unit 14, and a second data output control unit 16.
The first data output unit 10 includes an I/O line sense amplifier 100, a multiplexer 101, a pipe latch 102, a pre-driver 103, a data driver 104, and a data pad 105. The I/O line sense amplifier 100 amplifies data transferred from a memory cell and then outputs even data gio_ev<1> and odd data gio_od<1>. The multiplexer 101 receives the even data gio_ev<1> and the odd data gio_od<1> and then produces even multiplexed data mux_ev<1> and odd multiplexed data mux_od<1> by multiplexing the received data based on the data width. The pipe latch 102 which receives the even multiplexed data mux_ev<1> and the odd multiplexed data mux_od<1> sequentially outputs rising data rdo<1> and falling data fdo<1>. The pre-driver 103 latches and outputs the rising data rdo<1> and the falling data fdo<1> in synchronization with a rising clock pulse rclk_do<1> and a falling clock pulse fclk_do<1>, respectively. The data driver 104 drives the data outputted from the pre-driver 103 in order to transfer the data to the data pad 105.
Here, the data width is the number of data which are outputted by one read command. Typically, the data width is X32, X16 and X8. In data width of X32, 32 data are simultaneously outputted.
The data output control unit 12 includes a clock signal generating unit 120 and a clock pulse generating unit 122.
The clock signal generating unit 120 receives an external clock signal CLK, and produces a rising clock signal rclk in synchronization with a rising edge of the external clock signal CLK and produces a falling clock signal fclk in synchronization with a falling edge of the external clock signal CLK.
The clock pulse generating unit 122 produces the rising clock pulse rclk_do<1> and the falling clock pulse fclk_do<1> by delaying the rising clock signal rclk and the falling clock signal fclk for a predetermined time in order to adjust output timing of the rising data rdo<1> and the falling data fdo<1>.
The second data output unit 14 includes an I/O line sense amplifier 140, a multiplexer 141, a pipe latch 142, a pre-driver 143, a data driver 144, and a data pad 145.
The I/O line sense amplifier 140 amplifies data transferred from a memory cell and outputs even data gio_ev<2> and odd data gio_od<2>.
The multiplexer 141 receives the even data gio_ev<2> and the odd data gio_od<2> and then produces even multiplexed data mux_ev<2> and odd multiplexed data mux_od<2> by multiplexing the received data based on the data width.
The pipe latch 142 which receives the even multiplexed data mux_ev<2> and the odd multiplexed data mux_od<2> sequentially outputs rising data rdo<2> and falling data fdo<2>.
The pre-driver 143 latches and outputs the rising data rdo<2> and the falling data fdo<2> in synchronization with a rising clock pulse rclk_do<2> and a falling clock pulse fclk_do<2>, respectively. The data driver 144 drives the data outputted from the pre-driver 143 in order to transfer the data to the data pad 145.
The second data output control unit 16 includes a clock signal generating unit 160 and a clock pulse generating unit 162.
The clock signal generating unit 160 which receives the external clock signal CLK produces a rising clock signal rclk in synchronization with a rising edge of the external clock signal CLK and produces a falling clock signal fclk in synchronization with a falling edge of the external clock signal CLK.
The clock pulse generating unit 162 produces the rising clock pulse rclk_do<2> and the falling clock pulse fclk_do<2> by delaying the rising clock signal rclk and the falling clock signal fclk for a predetermined time in order to adjust output timing of the rising data rdo<2> and the falling data fdo<2>.
As mentioned above, the conventional data output circuit includes the first data output control unit 12 to produce the first rising clock pulse rclk_do<1> and the first falling clock pulse fclk_do<1> in order to adjust the output timing of the data outputted from the first data output unit 10 and also includes the second data output control unit 16 to produce the second rising clock pulse rclk_do<2> and the second falling clock pulse fclk_do<2> in order to adjust the output timing of the data outputted from the second data output unit 14.
However, since the conventional data output circuit has a plurality of data output control units based on the number of data output units, the chip size is getting larger and larger with the increase of the output data and current consumption is also increased. Particularly, in case that the data width is X32, the increase of the size and current consumption imposes a burden on the semiconductor memory device design.